资源列表
clock1
- 多功能数字钟实现闹铃，整点报时，校时，仿广播电台报时功能-multifuntional digital clock written in verilog
i2c_master_model
- i2c仿真model,可用于整体的FPGA仿真系统,用于i2c slave 设计的正确验证-i2c simulation model, the FPGA can be used for the whole simulation system designed for the proper verification i2c slave
I2C_slaver
- I2C从端，用于接收master的控制信号 verilog-I2C from the side, for receiving master control signal verilog
SEED-FEM025
- 合纵达FPGA开发板，原理图V-4系列，包括powerpc-fpga
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
FPGA
- 软件无线电调制解调系统的研究及其FPGA实现-FPGA
dac121
- 采用verilog编写的高速串型DA芯片dac121驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type DA-chip dac121 driver code, occupation le small, high efficiency, the current I applied to more products
timer
- 这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。-This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, t
lcd12864
- 在nios当中，用sopc，编写的12864测试程序，绝对不是抄写的，希望对大家有用-Among the nios with sopc, written in 12864 test procedures, is definitely not copying, I hope for all of us
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
DataCap_XKL_sw_0309_UCGUI_fine
- 使用xilinx提供的xilkernel系统，五个任务，使用了信号灯和消息队列， 包含ucGUI,增加了自定义键盘和液晶屏的支持。-Using xilinx provides xilkernel system, including ucGUI, an increase of custom keyboard and LCD screen support.
FSK_MOD_my
- verilog语言设计的用于fsk调制的源码-verilog language design for fsk modulation source