资源列表
icmp
- VHDL implementation of ICMP protocol tested
VHDL_LCD1602
- 用FPGA来实现液晶LCD1602的读写显示操作的程序代码。-Using FPGA to implement reading and writing LCD1602 LCD display operation code.
eda
- 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the desi
sc_camera_01APR08
- 基于FPGA的CMOS 传感器的图像传输处理.整个设计还基于NIOS.-FPGA-based CMOS sensor Image Transmission. The design is also based on NIOS.
E8051_256
- This contains the main-level VHDL files required for an example complete, ready-to-use, FPGA/ASIC 8051 microcontroller. The corresponding main schematic can be found in the Schematics folder, and a technical descr iption of the e8051 core inter
jiafaqi
- 用Veriloge编的四位二进制加法器。用一个显示屏进行显示。-Veriloge series with four binary adder. With a display to display.
sram_512x16bit
- SRAM的控制器，与sopc集成，可直接使用，方便稳定高速，简单修改可适应于其他容量-SRAM Controller in SOPC
WM_8776
- WM8776控制模块，直接调用为24位、44.1KHZ采样和输出，开启耳机输出。如需更改可将DA，AD和控制模块分别独立-WM8776 control module, a direct call for the 24-bit, 44.1KHZ sampling and output, open the headphone output. For a change can be DA, AD and control modules separately
50604
- vhal语言数字时钟设计 fpga cpld -vhdl
videodigitalsignalscontroller
- 使用Verilog语言编写的SRAM源码，可以移植，方便51控制-failed to translate
test_bech
- verilog + testbench 文件的读写操作-verilog+ testbench
count100
- 用VHDL语言编写的100进制计数器，计数到99后清零-VHDL language with the binary counter 100, count to 99 after the clear