资源列表
lcd12864
- 在nios当中，用sopc，编写的12864测试程序，绝对不是抄写的，希望对大家有用-Among the nios with sopc, written in 12864 test procedures, is definitely not copying, I hope for all of us
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
DataCap_XKL_sw_0309_UCGUI_fine
- 使用xilinx提供的xilkernel系统，五个任务，使用了信号灯和消息队列， 包含ucGUI,增加了自定义键盘和液晶屏的支持。-Using xilinx provides xilkernel system, including ucGUI, an increase of custom keyboard and LCD screen support.
FSK_MOD_my
- verilog语言设计的用于fsk调制的源码-verilog language design for fsk modulation source
AMI
- 本代码是用verilog写的AMI码的编码的程序，简单易懂，经调试是正确的。-This code is written in AMI code with verilog coding procedures, easy to understand, after debugging is correct.
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
BPSK_track_10.23M_BD_IF46.52MHz
- in tracking programm，actualize communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result-communications between DSP and FPGA Besides produce ahead code present code late code and correlation
dds_final
- 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
DPLL_verilog_a
- 用verilog语言描写设计的全数字锁相环，pDF资料-With the verilog language to describe the design of all-digital phase-locked loop, pDF information
CPU11111
- altera提供的sdram ip核例程，简单易懂。采用burst8模式。 -altera provided by the sdram ip core routines, easy to understand. Using burst8 model.
viterbi
- verilog code for viterbi encoder and decoder
AUTO_START
- verilog 编写的代码 方便使用 能自启动的七进制计数器-verilog code written in easy to use can be self-starting of the seven binary counter