资源列表
NIOS_lcd12864
- 基于NIOS II系统的12864LCD的读写。-12864LCD NIOS II system based on reading and writing.
div
- 利用Ｖerilog实现定点数的除法，在此基础上可考虑实现定点数的除法-Using Verilog to achieve set division points, on this basis can be considered fixed points of the division to achieve
_8259A
- 8259A是专门为了对8085A和8086/8088进行中断控制而设计的芯片，它是可以用程序控制的中断控制器。单个的8259A能管理8级向量优先级中断。在不增加其他电路的情况下，最多可以级联成64级的向量优先级中断系统。8259A有多种工作方式，能用于各种系统。各种工作方式的设定是在初始化时通过软件进行的。 在总线控制器的控制下,8259A芯片可以处于编程状态和操作状态.编程状态是CPU使用IN或OUT指令对8259A芯片进行初始化编程的状态- 8259A is designed t
DigitalSignalGenerator
- 多功能信号发生器，实现4种常见波形正弦波、三角波、锯齿波、方波的功能。并且输出信号的频率范围为100Hz~200KHz,输出频率可以调节；可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出，具有显示输出波形、频率的功能。-Digital Signal Generator
2-fsk
- 2-fsk调制解调的fpga实现。two-fsk为调制程序，fsk-two为解调程序。-2-fsk modulation and demodulation of fpga implementation. two-fsk for the modulation process, fsk-two for the demodulation process.
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machine design comparison
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
data_interleaver_ise10migration
- ofdm通信系统交织的Verilog实现，源码中有两个错误，第二处少了一个begin 第一处为全角半角，自己写一下就行-ofdm data_interleaver
amp
- 实现乘法和加法功能的Verilog HDL 硬件描述语言-Multiplication and filtering functions to achieve the main frame
MII_timing
- 用FPGA实现MII的数据传送时序控制,方法简单实用，设计及其精巧-implementation of MII data transmission’s timing control
vhdl
- 伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
key44
- VHDL描述4*4标准矩阵键盘扫描读取并点亮对应的LED灯，试验已经通过。可能还差一些按键的防抖，但不影响整体测试-VHDL descr iption of the standard 4* 4 matrix keyboard scan read and the corresponding LED lights lit the pilot had been adopted. Stabilization may be even worse some of the buttons, it does n