资源列表
chengfaqi
- VHDL24*24位无符号乘法器，采用的是18*18结构-VHDL24*24-bit unsigned multiplier, used in the structure of 18* 18
beep
- 基于VHDL的蜂鸣器实验方案，已经通过验证，可放心使用-VHDL-based buzzer experimental program has been verified, safe for use
DA_TLC5620
- 基于VHDL的DA--TLC5620实验解决方案，可放心使用-Based on VHDL for DA- TLC5620 test solution can be freely used
PCIBridge
- pci bridge的verilog实现。-the verilog implemetion of PCI Bridge
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
multiplier
- 个人收集的各种乘法器vhdl源代码，都经过验证，可以直接使用的。-Collected a lot of multiplier vhdl source code
booth_mult
- VHDL code for Booth multiplier for 32bit input
sin
- QUARTUSS||环境下的简易正弦信号发生器的设计，VERILOG 代码，用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
floatmultiplierVHDL
- 32为浮点数乘法的vhdl源代码，嵌入式系统中有可能会用到，基于fpga硬件实现-32 for the floating point multiplication vhdl source code, embedded systems may be used, based on fpga hardware
duoxiang
- 多相滤波器的FPGA实现结构，基于QuartusII8.1实现-Polyphase filter FPGA implementation structure to achieve based on QuartusII8.1
noise
- 基于FPGA的噪声产生电路，用MATLAB设计噪声仿真程序，产生仿真数据的方法。并利用FPGA模拟信号。其中有详尽的matlab仿真程序，FPGA仿真结果以及总的设计报告。-Noise generating circuit based on FPGA, using MATLAB simulation program designed noise, resulting simulation data. Analog signal using the FPGA. Which detailed mat
KD-CPU
- 计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.