资源列表
2-fsk
- 2-fsk调制解调的fpga实现。two-fsk为调制程序，fsk-two为解调程序。-2-fsk modulation and demodulation of fpga implementation. two-fsk for the modulation process, fsk-two for the demodulation process.
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machine design comparison
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
data_interleaver_ise10migration
- ofdm通信系统交织的Verilog实现，源码中有两个错误，第二处少了一个begin 第一处为全角半角，自己写一下就行-ofdm data_interleaver
amp
- 实现乘法和加法功能的Verilog HDL 硬件描述语言-Multiplication and filtering functions to achieve the main frame
MII_timing
- 用FPGA实现MII的数据传送时序控制,方法简单实用，设计及其精巧-implementation of MII data transmission’s timing control
vhdl
- 伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
key44
- VHDL描述4*4标准矩阵键盘扫描读取并点亮对应的LED灯，试验已经通过。可能还差一些按键的防抖，但不影响整体测试-VHDL descr iption of the standard 4* 4 matrix keyboard scan read and the corresponding LED lights lit the pilot had been adopted. Stabilization may be even worse some of the buttons, it does n
TERASIC_Binary_VGA_Controller
- 友晶公司提供的VGA Controller的IP核设计。针对的是DE2_70开发板。-Friends of the crystal provides the VGA Controller of the IP core design. Development board for the DE2_70.
IIR(vhdl)
- 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
liushuideng
- 这个是eda开发流水灯实验的示范程序，在试验箱上运行成功-This is eda development of light water experimental demonstration program, run successfully in the test chamber
fpga_mcu_communication
- 本压缩文件是51单片机与Altera_Cyclone fpga串口通信程序，经过硬件实际测试验证可用。-This compressed file is 51 and Altera_Cyclone fpga serial communication program, available through the actual test hardware.