资源列表
fifo2
- 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
lcdcontrol_verilog
- LCD控制器的VERILOG实现 对学FPGA的人说很有用的-the implemation of LCD control
ADPCM
- ADPCM ENCODER and DECODER
m-mtip-10_100_1000_ethermac
- 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
MCU8951
- 该文档中是在FPGA中嵌入单片机核的一个设计系统，而且具有VHDL编写的51核源程序。-The document is embedded in the FPGA design system of a microcontroller core, and has 51 nuclear source code written in VHDL.
qiangda
- EDA课程设计智力抢答器 四路抢答器的设计以及程序和视屏 软件运行环境是：Quartus 9.1-EDA curriculum design intelligence Responder four answering device design and process and Screen software operating environment is：Quartus 9.1
bujindianjikongzhi
- 在quartus II下用verilog编写的步进电机位置控制程序，其中包含7个子模块和1个顶层模块，本程序层次清晰、功能明确。乃个人收藏，推荐大家下载学习！-Verilog in quartus II, prepared under the stepper motor with position control program, which contains seven sub-modules, and a top-level module, the program-level clarity
8-layerelevatorrunprogram
- 用VHDL代码编写的8层电梯工作过程，有详细的注释-VHDL code is written with 8-layer lift the working process, with detailed notes
Verilog
- 基于Verilog的编码用BOOTH算法和移位相加实现乘法运算-BOOTH Algorithm with multiplication
NIOS_lcd12864
- 基于NIOS II系统的12864LCD的读写。-12864LCD NIOS II system based on reading and writing.
div
- 利用Ｖerilog实现定点数的除法，在此基础上可考虑实现定点数的除法-Using Verilog to achieve set division points, on this basis can be considered fixed points of the division to achieve