资源列表
ModelSim-code
- 用modelsim以及systemC发在一些小例子和使用心得-Made with modelsim and systemC use in some small examples and experiences
pwm_last
- 输出PWM波的资料,可以用来输出正弦波,三角波等-PWM wave output data
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例,仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码(加/减)计数显示器(ADD-SUB)。 二、指示灯循环显示器(LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可
taxi
- 出租车自动计费器,使用verilog hdl语言编写,计费包括起步费、里程费、等待费,并利用八位数码管显示。-Automatic meter taxi, using verilog hdl language, including start charging fees, mileage fees, waiting costs, and use eight digital display.
DDS__FPGA
- 基于FPGA的DDS信号发生器设计,包含Quartus 的工程,打开即可使用,Verilog 语言编写!-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
dif_jiaorao
- FPGA适用的加扰和差分编码程序,VHDL描述,适用于Xilinx FPGA-for Xilinx FPGA
verilog_cordic.tar
- 用verilog实现cordic算法。支持多模,有vecter和rotate模式。支持多种输出-Algorithm to achieve cordic with verilog. Multi-mode, there vecter and rotate mode. Support for multiple output
XAPP868
- E1/T1时钟提取和恢复源码 是xilinx的IP源码-E1/T1 clock recover code,it is xilinx s IP code
I2C
- I2C/IIC 总线接口驱动,在Altera和Xilinx的FPGA上跑过,Verilog编写,Craftor原创。V1.1。代码中还包含了24C02的读写测试程序,可直接用。-I2C/IIC Bus Driver, written in Verilog, v1.1. By Craftor
354545
- 用VHDL实现出租车计价器,此程序已通过验证-VHDL implementation with a taxi meter, this procedure has been verified. .
TestAD9709_AD9288_Verilog
- 使用Verilog语言控制高速AD9288 Ad9707-Verilog language control using high-speed AD9288 Ad9707
fft3
- 是用verilog写的FFt源码,通过编译基本是正确,希望对大家有所帮助-Is written FFt verilog source code, compile basic right, we want to help