资源列表
fir_16
- 用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
CORDIC_design_digital_computers
- CORDIC算法设计的数字计算机，基于Verilog设计-CORDIC algorithm based on the design of digital computer, Verilog design code
Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
12345
- 本程序为直线插补程序,运用在数控机床上.RAR-This procedure is linear interpolation procedure, used in CNC machine tools. RAR
butterfly1
- FFT蝶形运算单元程序，可用于OFDM,以及任何相关数字信号处理的设计中-FFT butterfly processor program can be used in OFDM, as well as any relevant design of digital signal processing
core
- HDLC core, standalone controller with buffers. vhdl source code
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
QPSK
- qpsk调制解调的VHDL源代码，已调试成功，可放心使用。-qpsk modulation and demodulation of the VHDL source code ，which has been debugged and can be freely used.
SPI_verilog_vhdl
- spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi
FPGA_SPI.ZIP
- 实现了FPGA以SPI协议传送和接受16位数据。传送过程无需Nios核干预-SPI protocol to achieve the FPGA to send and receive a 16-bit data. Nios nuclear transfer process without intervention
FPGA_design
- Altera+FPGA／CPLD设计基础篇和高级篇.pdf，详细讲解FPGA的设计过程及应用-Altera+ FPGA/CPLD Design Basics and advanced articles. Pdf, explain in detail the design process and application of FPGA
ASIC-SYNOPSYS
- 芯片设计综合经典书籍 design compiler primetime-asic synthesys