资源列表
Synopsys-RTLSystemC
- synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料-synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials
ALU
- 用VHDL硬件描述语言写的ALU设计，有加法，减法，乘法和除法等计算功能。-VHDL hardware descr iption language used to write the ALU design, there are addition, subtraction, multiplication and division such as computing.
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
fir_16
- 用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
CORDIC_design_digital_computers
- CORDIC算法设计的数字计算机，基于Verilog设计-CORDIC algorithm based on the design of digital computer, Verilog design code
Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
12345
- 本程序为直线插补程序,运用在数控机床上.RAR-This procedure is linear interpolation procedure, used in CNC machine tools. RAR
butterfly1
- FFT蝶形运算单元程序，可用于OFDM,以及任何相关数字信号处理的设计中-FFT butterfly processor program can be used in OFDM, as well as any relevant design of digital signal processing
core
- HDLC core, standalone controller with buffers. vhdl source code
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
QPSK
- qpsk调制解调的VHDL源代码，已调试成功，可放心使用。-qpsk modulation and demodulation of the VHDL source code ，which has been debugged and can be freely used.
SPI_verilog_vhdl
- spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi