资源列表
sram_test_OK
- 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图-Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for
lab28
- 采用5级流水线MIPS微处理器设计，实现32位流水线的算数、逻辑、以为等指令-pipeline MIPS
AD_sampling
- 基于Verilog的AD采样FPGA程序,如果使用的话，FPGA接口重新设置即可-AD Sampling verilog program that is based on FPGA，if used，the IO Pins of FPGA should be redifined
hdl
- spi verilog ad9628-spi verilog ad9628
code_lock_vhdl
- 在ISE环境下用vhdl写的一个密码锁程序。下载到xilinx 公司的 spartan6 的板子上验证过的，也有仿真代码。主要就是几个状态之间的转换，用了一个moore状态机。-In the ISE environment using vhdl to write a lock program. Downloaded to the board spartan6 xilinx' s proven, there are simulation code. Mainly the conversion
v
- Synthetisable verilog of compact crypto algorithms: RC4, TEA, XTEA, XXTEA. A faster but, more resource hungry version for RC4 and XXTEA is included.
sram_test
- 用Verilog写的SRAM测试程序，先向SRAM里面写数据，然后再将数据读出来做比较。-Written using Verilog SRAM test program, which Xianxiang SRAM write data, and then read out the data for comparison.
spdif
- spdif接口，用于高音质音频数据传输。代码实现了数据接收和发送。-spdif interface for high-quality audio data transmission
Motion_control
- 基于FPGA的运动控制系统设计，包含位置、速度控制等-motion control
ml605_pcie_x4_gen2
- 使用与xilinx的ml605套件的pcie核程序，芯片 型号是v6系列的4通道的pcie设计。内部包括pcie ip核和用户端程序。已亲测。-Xilinx ml605 using the kit pcie nuclear program, chip model is v6 series of 4-channel pcie design. Internal including pcie ip core and client programs. It has been pro-test.
Limi
- 用VHDL设计一个6位二进制计数器：用VHDL设计一个6位二进制计数器-VHDL design with a 6-bit binary counter
tb_axi4
- 介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.