资源列表
CFO
- zedboard/AD9361平台进行无线收发，在接收端进行频偏估计和补偿的Verilog参考代码。-zedboard/AD9361 platform for wireless transceiver, the receiver frequency offset estimation and compensation, you can refer to the Verilog code.
myfpga
- 这个是经典的FPGA的相关的乘法器，除法器的代码，还有别的可用的资料，都是网络上攒的，并且真的是非常经典-This is a classic of the relevant multiplier divider FPGA code, as well as other available information, are saved on the network, and really is very classic
value_to_ascii
- 使用Verilog HDL 进行数值与字符ASCII码的转化，实现串口正确显示字符，编程环境Quartus -Use Verilog HDL to numerically with ASCII characters transformation, realize serial display character correctly, Quartus ii programming environment
FM_T
- 一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发-A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development
Quadrature-modulate-design
- FPGA正交调制设计Verilog程序代码-FPGA Orthogonal modulation design procedure code
basys3_basic_demo
- Basys 3 开发板的自带程序，包括LED 数码管 按键 鼠标等各项功能的演示。-Basys 3 development board comes with the program, including the LED digital control buttons and other functions of the mouse.
ddr_top
- verilog语言ddr3读写程序，axi总线协议，用于ddr3读写测试-ddr3 read and write
fifo_mem
- 同步FIFO，IP核生成ram，已验证可用。-Synchronous FIFO, IP core generation ram, verified available.
matrix-inversion
- 基于Systolic的上三角矩阵求逆的实现，含有详细的verilog代码，并给出详细的注释-upper triangular matrix inversion
CoreUartTest
- Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
cpri
- 基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码-Cpri interface based on verilog code, support various rate free switch, production products the actual application code
SRIO-phy-code
- SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development