资源列表
VHDL-Gray-code
- 基于vhdl格雷码设计代码，调试过没错误。-Gray code design based on VHDL code, debugging didn t mistake.
AD9640
- 这是用erilog语言编写的控制100M/150M高速AD9640的程序，适用于FPGA，亲测可用，供参考。-this is a program for FPGA to control AD9640, which is useful by verilog.
PCIe_CIVGX_AVST_On_Chip_Mem
- Altera公司的pcie核，附有调试用的驱动和上位机-pcie hard ip of altera, with driver and debug GUI
norflash-model
- norflash verilog hdl simulation model
mouse_kit
- 实现难度可调（6级，速度不同）的简单打地鼠游戏。开发板上的led灯代表地鼠，按键代表锤子。此程序代码可直接执行，适合初学者VHDL入门。 源码中，divider为分屏器；key_scan为按键扫描；random产生随机数；music为背景音乐播放模块；manage为主程序模块。-Adjustable implementation difficulty (6 level, different speeds) simple whack-a-mole game.The led lights on
adder8
- 8位加法器源代码，vivado实现编写。-8 adder Source, vivado achieve write.
AFE0064
- AFE0064模拟前端芯片代码，使用verilog语言实现。-TI AFE0064 analog-front-end code with the verilog language
music
- 利用PWM使蜂鸣器产生音乐的verilog源代码及《友谊地久天长》的电路设计-Generates a PWM buzzer music verilog source code and Auld Lang Syne circuit design
H.264-for-FPGA
- This Book describe about H.264 encoder using Verilog HDL
TSMC
- TCBN65LPBWP7T VERSION 200A tsmc CLN65LP : 65nm CMOS LOGIC Low Power
Random_Derandom
- 通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。-Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.
Interleaver_Deinterleaver
- 通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。-Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.