资源列表
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
dif_jiaorao
- FPGA适用的加扰和差分编码程序，VHDL描述，适用于Xilinx FPGA-for Xilinx FPGA
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
iir_par
- IIR parallel VHDL FPGA
pci9054
- PCI读写控制程序 PCI9054与SRAM连接-PCI9054 PCI read and write control procedures connected with the SRAM
FIFOMXN
- 该VHDL描述的是一个简单的先进先出存储器-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
S-35390A-IIC
- 用GPIO口模拟IIC接口，可以发送和接收多个字符，参照S-35390A RTC芯片命令格式编写。-use the GPIO pin to simulate the IIC interface, based on the S-35390A RTC clock chipset command format, can send or receive single/multi byte command/data.
is61lv25616
- 以is61lv25616为例，用verilog实现的SRAM-SRAM implemented verilog
Four-ways-of-contest
- 基于vhdl硬件设计语言而设计的四路抢答器-Based on VHDL designed hardware design language road 4 contest device
Addr_Generator
- 其中start是开始信号，上升沿启动控制单元；CLK是工作时钟；CtrlAddr是读取控制字时的地址；CtrlData是读取的控制字；Reading是读信号；EOP是本次AD采样完成信号，只有当AD1和AD2均完成后EOP才为高；EN是允许信号，启动分频器、地址发生器；N是分频系数；Addr1和Addr2分别是AD1和AD2数据存储的起始地址；NUM1和NUM2分别是采样点数。 控制字分别表示分频系数为2，AD1起始地址为1，采样点数5，AD2起始地址为3，采样点数为4。 -Where
FPGA-drive-12864
- FPGA驱动12864液晶,一般可以显示我们想显示的，只要相应的适当修改。-The FPGA drive, can generally 12864 LCD display we want to show, as long as the corresponding appropriate modification.
Dac714
- dac714的控制程序，包括spi数据通信，转换控制-dac714 control procedures, including the spi data communications, switching control