资源列表
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
FT245
- 在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
PWM-control-LED--
- PWM控制LED灯亮度程序 提供的代码仅供参考 在使用时需要自己一定的修改添加-PWM control of LED brightness provides the code for reference in the use of certain modifications need to add their own
VHDL-language
- 用VHDL语言完成4位锁存器、测频控制器的设计-VHDL language to complete 4-bit latch, the measured frequency controller design
BCH-dec
- 基于C的BCH纠错码研究，已经做了调试，和你好用。-C-based study of the BCH error correction code, debugging has been done, and Hello to use.
test5
- 用VHDL设计8位算术逻辑运算器，并将运算结果显示通过俩个七段数码管显示-Design with VHDL 8-bit arithmetic and logic devices, and computing results show that by two seven-segment LED display
configue_dac
- AD5624模拟数字转换芯片SDI接口配置代码-AD5624 analog-digital converter chip SDI interface configuration code
pinlv
- 用stm32测fpga输出的频率，带宽可达1Hz-1MHz-Stm32 with the frequency of fpga output, bandwidth of 1 Hz-1 MHz
TLV5618
- TLV5618 DA转换程序 怎样用Verilog语言实现。-TLV5618 DA Converter， how to use Verilog language realize it。
TEST3
- T0发出周期为2S的脉冲，T1做计数器计数，并动态扫描显示计数脉冲数。-Given period of 2S T0 pulse, T1 do counter, and dynamic scanning display count pulses.
hx711
- 基于FPGA用verilogHDL语言设计的HX711驱动程序，本人设计，驱动成功-a code used for move hx711,which based on FPGA by verilogHDL
key_test
- verilog HDL编写的在quartusii环境下的24秒倒计时代码-verilog HDL the quartusii environment in the 24 seconds countdown code