资源列表
rgb2ycrcb
- 基于fpga的RGB转YcRcB源程序，verilog语言-Fpga-based RGB to YcRcB source, verilog language
data_scramble
- 用verilog 语言编译数字通信中的符号扰码，预防长1或长0的出现-a great complied code of data sramble for OFDM
CP_adder
- 用verilog 语言实现数字通信中最先进的技术之一中的OFDM技术中的添加循环前缀，可以减少码间干扰，并实现符号同步-a great complied code of cyclic prefix for OFDM which is good for intersymbol interference and inter channel interference
bt656_decode
- bt656 标准的解码 verilog 语言-bt656 decode
gwnseq
- verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence
ad7606_control
- ad7606 fpga接口 程序 ，实现ad7606的串口 读写，数据缓存-ad7606 controller,writen by verilog.
hpi
- 实现FPGA控制DSP的HPI接口，使用verilog接口-Achieve FPGA DSP HPI interface control, use verilog interface
bt656_to_yuv422
- 从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式-bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal
cdr
- 数据时钟恢复，采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation
ADC_handle
- 针对ADC器件AD9226的数据采集处理流程，针对手册时序做的有效数据输出控制。Verilog HDL- ADC AD9226 data acquisition device for processing flow for the manual timing do valid data output control.Verilog HDL
fifo_mem
- 同步FIFO，IP核生成ram，已验证可用。-Synchronous FIFO, IP core generation ram, verified available.
soft_hdmi
- 模拟adv7619 hdmi 4k视频输出信号-Analog adv7619 hdmi 4k video output signal