资源列表
cic10_sec5
- 抽取因子可调，四级梳状滤波器，在数字下变频中会使用到(The decimation factor is adjustable, and the four stage comb filter is used in digital down conversion)
VerilogHDL的135个经典设计实例
- Verilog HDL编程设计学习程序例子，含详细说明(Verilog HDL programming design learning examples, including detailed descr iption)
adder_1bit
- adder_1bit using language systemc
adder_4bit
- program using systemc synthesis GCD
GCD
- synthesis GCD using systemc
naisenyao
- Join repetitive control, Foreign materials inside the source code, Two-way PCS control simulation.
ddr3_test_top
- DDR3 test code 測試用的代碼 學習用,簡單的使用DDR3(DDR3 test code for learning verilog code study.)
8051-master
- 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU inte
电梯控制器报告(Verilog实现)
- 实现一个简单的电梯控制器,能够完成一个四层电梯的控制(The realization of a simple elevator controller, to complete a four storey elevator control)
test56_PWM3
- VHDL 3 phase of PWM microsemi project
test59_TRIGU
- VHDL generating of trig signal microsemi project
test60_TRIGD
- VHDL generating of trig down signal microsemi project