资源列表
datasheet
- 可测试EMIF接口，包含读写两种时序,1394协议，LM75A(EMIF interface can be tested, including reading and writing two timing)
BreastCancer (1)
- breast Cancer Classification
spartan6_ibis
- Xilinx Spartan-6 FPGA 信号完整性 分析仿真模型(Xilinx, Spartan-6, FPGA signal integrity Analytical simulation model)
spi_MasterSlaver
- 实现3种模式SPI主从模块功能设计，数据位宽8bit，最大SPI时钟频率支持112MHz，采用FSM设计实现。经本人亲测可用，使用于Spartan6——45T系列芯片；(To achieve three modes SPI master and slave module function design, data bit width 8bit, the maximum SPI clock frequency support 112MHz, using FSM design. Prepared b
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较
VHDL数字电路设计教程
- FPGA经典教程，vhdl经典教程，从入门到精通(FPGA classic tutorial, VHDL classic tutorial, from entry to the master)
夏宇闻数字逻辑设计
- 夏文宇经典FPGA教程，手把手教你学会FPGA(Xia Wenyu classic FPGA tutorial, hand taught you to learn FPGA)
Desktop
- I2C,测试代码，经过验证调试与，这个测试代码发现是可用的(I2C, test code, verified debugging and, this test code discovery is available)
prj_ex_2
- 锁存器的写法仿真和方法，经过具体的仿真和优化，发现代码完全可用(The method and simulation of the locking device are simulated and optimized, and the code is found to be fully available)
prj_ex_1
- 基本工程写法仿真和方法，经过具体的仿真和优化，发现代码完全可用(The method and simulation of the locking device are simulated and optimized, and the code is found to be fully available)
prj_ex_3
- 状态机基本工程写法仿真和方法，经过具体的仿真和优化，发现代码完全可用(State machine basic engineering writing simulation and method, after specific simulation and optimization, find out the code is completely available)
prj_ex_4
- 移位寄存器的详细剖析，经过具体的仿真和优化，发现代码完全可用(The detailed analysis of the shift register, through concrete simulation and optimization, found that the code was fully available)