资源列表
LCD
- LCD1602驱动 verilog编写 下载到deii板子(LCD1602 Verilog FPGA DEII)
lab1
- 用半加器搭建全加器 使用Verilog语言(Using a half adder to build a full adder, using the Verilog language)
lab2
- 算数逻辑运算单元 使用verilog编写(Arithmetic logical arithmetic units are written in Verilog)
lab3
- booth算法移位乘 使用verilog(Booth algorithm shift multiply Verilog)
fsm
- 有限状态机fsm 二段式编写 verilog(Finite state machine, FSM, two sections, verilog)
8116
- LCMV optimization design array signal processing, Very suitable for the study using computer vision, Using high-order cumulants of MPSK signal modulation recognition.
hdl-2014_r2.tar
- AD9361 IP 核，Linux版本，Vivado2014.2(AD9361 IP core, used on Linux, Vivado2014.2.)
hdl-2014_r2
- AD9361 IP核，Windows版本，Vivado2014.2(AD9361 IP core, used on Windows, Vivado2014.2)
hdl-2015_r2.tar
- AD9361 IP核，Linux版本，Vivado2015.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2015_r2
- AD9361 IP核，Windows版本，Vivado2015.2(AD9361 IP core, used on Windows, Vivado2015.2)
hdl-2016_r2.tar
- AD9361 IP核，Linux版本，Vivado2016.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2016_r2
- AD9361 IP核，Windows版本，Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)