资源列表
Serial to parallel vhdl
- SERIAL TO PARALLEL VHDL CODE
Writing Testbenches using System Verilog
- Material to learn how to use system verilog and how to write testbenches for verification.
3M
- 在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal
8
- filter fir tap implementation
xi
- xilinx screenshot vhdl verilog
file2
- factorial file for the fortran pascal
OSVersion
- os version Descr iption
fifo_test
- fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
DIGITALCLOCK
- 多功能数字种 可实现校时 闹钟 整点报时等功能(Multi-function digital species can realize the function of time alarm clock and other functions)
m60
- 使用verilog实现模六十计数即0-1-2-3-4-5-.......-59-0-1-2的功能。(Use Verilog to realize the function of the mode sixty count, 0-1-2-3-4-5-....-59-0-1-2.)
DE10-Lite_v.2.0.1_SystemCD
- DE10-Lite_v.2.0.1_SystemCD
DE10-Lite_ControlPanel_v.1.0.2
- DE10-Lite_ControlPanel 调试面板(DE10-Lite_ControlPanel test panel)