资源列表
squareLoop
- 利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)
quartus和modelsim中使用mif和hex文件1
- quartus和modelsim中使用mif和hex文件1(fpga modelsim mif hex)
v
- statistical signal processing,verilog
src
- v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
MaxMovie 老干妈
- 演示demo 更清晰更明了 快速便捷 简洁。(The demo demo is clearer and clearer and faster and simpler.)
alu
- Code to synthesize Arithmetic Logic Unit
ActelFPGA
- ACTEL FPGA system is introduced, the older the FPGA
SystemVerilog_Synopsys
- systemverilog introduction by synopsys
verilab_dvcon2012_uvm_cooper
- Getting Started with UVM by Verilab
PPM
- 对4比特二进制数据进行PPM调制，位宽可修改(PPM modulation for 4 bit binary data)
DVCon_Europe_2015_T01_Presentation
- Advanced UVM Tutorial by Verilab
《Verilog HDL设计与实战》配套代码(1)
- 《Verilog HDL设计与实战》配套代码 verilog源程序(Verilog HDL design and actual combat code Verilog source program)