资源列表
08167129pllverilog
- PLL CONFIGUARTION USING FOAGA IN VERILOG LANGUAGE
17416335PLLfpgapaper
- PLL CONFIGURATION USING FPGA IN VERILOG LANGUAGE
31767694FPGA-PLL
- PLL CONFIGURATION USING FPGA
37148515LC
- PLL CONFIGUARTION USING FPGA
aes-master
- aes master by vhdl code and decode
aes128-hdl-master
- Verilog AES hdl key 128 bit code and decode
aes-project-master
- aes project vhdl FPGA
counter
- 基于FPGA平台的，计数器的简单实现过程(Code based on FPGA, a realization of VHDL/counter)
Vivado_2037
- vivado 2015.4 lisence
seg_1
- 计时模块，数码管显示，格式：时，分，秒。用于初学者参考学习(Time module, digital tube display, format: time, minute, second)
oc8051
- oc8051源码 verilog形式 已在FPGA验证(Source code of oc8051)
DDS30k
- 在quartus开发平台基于直接数字频率合成技术利用Verilog语言实现正弦信号和三角波信号发生(Verilog was used to generate sine and triangle wave signals based on direct digital frequency synthesis in quartus development platform.)