资源列表
can-sja1000
- CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。-The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.
yuandengke
- 袁登科的永磁同步电机一书书，里面的全部源代码，-yuandengke pmsm of book matalb
DHT11_verilog
- 基于FPGA的DHT11使用代码，本人已经调试过，可用。-FPGA-based DHT11 use the code, I have debugged and available.
QAM_FPGA
- QAM调制，基于FPGA的实现，包含有乘法器模块、升降余弦滤波器模块、QAM序列生成模块-QAM modulator,the implementation based on FPGA,include MUL、FIRCOS and QAM generate
apbtoaes128_latest.tar
- AES加密算法verilog代码实现，基于APB总线接口数字IP，包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
QAM
- 16QAM调制 基于vivado环境下16QAM调制 -16QAM modulation
FLIR-LEPTON-CameraFPGAdriver
- FLIR LEPTON远红外摄像头FPGA驱动程序-LEPTON FPGA far infrared camera FLIR driver
ov5640
- fpga控制CMOS相机ov5640采集图像，包括相机配置，ddr缓存，vga显示三个模块。直接可用-fpga control CMOS camera ov5640 capture images, including camera configuration, ddr cache, vga three display modules. Directly available
PowerSum
- 此模块的主要功能是实现距离单元数据的功率和求解，即把输入信号的实部、虚部分别 求解平方和，然后把两者相加，每个距离单元内有1024个复数数据 接口： clk 时钟信号，50MHz rst_n 复位信号，低电平有效 PowerSumInEn：功率和模块输入信号的有效信号，1bit，高电平有效 PowerSumInRe：功率和模块输入信号的实部，8bit PowerSumInIm：功率和模块输入信号的虚部，8bit PowerSumOut： 功率和模块输出
dht11
- DTH11温湿度模块的verilog HDL 代码-The verilog HDL code of DTH11
FPGA_phase_lock_demodulation
- FPGA 用Verilog语言实现数字锁相解调系统，包含了正交的DDS函数发生器和相应的AD驱动-FPGA digital demodulation system in Verilog lock, comprising a DDS orthogonal function generator and driving the corresponding AD
fft_ex1
- 基于verilog的FFT设计，使用vivado作为开发平台-Verilog based on the FFT design, the use of vivado as a development platform