资源列表
CSI2TXReferenceDesign
- 适用于MIPI-CSI2的并串转换模块，可将RGB、YUV等格式的图像信号转为兼容MIPI数据通道的串行数据信号(It is suitable for the parallel conversion module of MIPI-CSI2, which converts the image signals in RGB, YUV and other formats into serial data signals compatible with MIPI data channels)
Verilog的150个经典设计实例
- verilog例程，对于新手学习verilog很有帮助(Verilog routines, for beginners to learn Verilog helpful)
float_2_int.v
- 最全的，最简单，32位浮点数转整数，32位整数转浮点数，直接可以移植，已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
Xilinx新一代FPGA设计套件Vivado配套资料
- verilog经典教程，入门者的必选书籍，非常实用，可以学习到很多的知识(verilog classic tutorial, entry must be books, very practical, you can learn a lot of knowledge)
W5300_IF
- 实现FPGA与W5300 芯片的百兆以太网通信 ，实际项目中应用很多(Fast Ethernet communication between FPGA and W5300 chip, the actual project in many applications)
4Bit超前进位加法器门级电路设计与仿真
- 用门级网表的方法对4Bit超前进位加法器门级电路连接关系用verilog语言进行描述(The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist)
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
temper_test
- 通过Verilog实现用DS18B20温度传感器用MAX7219驱动8个数码管显示。（MAX7219驱动程序也在里面）。实验用EP4CE22F17芯片实现。(Through Verilog realize with DS18B20 temperature sensor, drive 8 digital tube display with MAX7219. (the MAX7219 driver is also inside). Experiment with EP4CE22F17 chip.)
sdram_control
- SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
CIC_Filter_Module
- 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)