资源列表
DEF
- 一个简单的始终触发器的代码 另外包括测试验证程序和输入码数据
count
- 用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
ring
- Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
clk_div
- 一个时钟分频模块,in verilog hdl-clock division module in verilog hdl
VGA
- 实现了vga的功能，采用文本编辑的，源代码，有利于初学者对FPGA上部分模板学习-Achieved a vga function, using a text editor, source code, help for beginners to learn on the FPGA on the part of the template
clk_div2_4_8_16_32_64_128
- Divide by 2,4,8,16,32,64,128 clock divider
Shfit8bit
- 8位移位寄存器的vhdl设计，经过仿真验证，程序简单易懂，易于初学者借鉴-8-bit shift register vhdl design, through simulation, the program is easy to understand, easy for beginners learn from
clock-divider
- clock generator vhdl code
led
- 流水灯,就是利用verilog语言实现一个简单的流水灯，主要是让大家勒戒一下结构-the led is flow water
mod_n_counter_tb
- MODULO N COUNTER VHDL
FIR_lowpass
- 一种实用的基于FPGA的8阶高斯低通FIR滤波器-A practical 8 order gaussian low-pass FIR filter based on FPGA
Communication
- TMS320F28335与CPLD通讯，scib-TMS320F28335 and CPLD communication