资源列表
ISE8.1_loopback
- 硬件平台为Xilinx Spartan3e，编译软件为ISE8.1，实现了九针com口通信，键盘输入回显，switch控制LED功能。-hardware platform for Xilinx Spartan3e, compile software ISE8.1. achieved nine needles com port communication, a return to the keyboard input, LED control switch function.
cache
- 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
m15
- 扩频通信M序列,编码,通用VHDL语言-M sequence spread spectrum communication, coding, generic VHDL
m511new
- 扩频通信M511序列,编码,通用VHDL语言,用于相关-M511 sequence spread spectrum communication, coding, generic VHDL, for related
8bit_MCU
- 8BIT MCU 的VERILOG代码实现，具有一定的参考价值-8BIT MCU verilog code realized, with some reference value
VerilogHDLTestBenchPrimer
- 讲解Verilog 的testbench的书写方法。-on Verilog testbench writing.
USB_I2C_MAC_FPGA_Code
- 《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design
lcdVHDL
- ＶＨＤＬ语言 用来实现对LCD的控制，实现显示功能-VHDL language used to achieve the right LCD control, achieving display function
FSKVHDL
- VHDL语言编写的程序，实现FSK调制与解调及仿真-VHDL prepared by the procedures, FSK modulation and demodulation and Simulation
ADC0809VHDL
- VHDL语言编写的程序，实现控制ADC0809的工作 -VHDL prepared by the procedures, the control Connection between ADC 0809
FIR_beh
- FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
VHDL_of_example
- 此 为 VHDL 的示例程序,由于最近毕业设计要求使用这个编程,自己收集并整理了一些,供学习使用,希望和大家共同进步,有兴趣的也希望能和我一起讨论交流-this as examples of VHDL procedures, due to the recent graduation design requirements using the program, their collection by some for learning, hope and common progress. Inte