资源列表
chuankou
- FPGA和单片机的串口通信资料，本代码是用VHDL写的。-FPGA and the microcontroller serial communication of information, the code is written in VHDL.
verilogforelevater
- 本代码主要用于实现利用verilog编码八层电梯的自动控制。利于初学者学习参考-This code is primarily used to implement the use of automatic control verilog coding eight-story elevator. Reference to help beginners learn
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
DS1302
- 本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可-This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays
DecoderAudio
- 本程序为SDI的音视频分离Verilog程序，信号通过分离后，可以分离出视频和音频信号。-This procedure for the separation of SDI audio and video Verilog program, the signal after the separation, can be isolated video and audio signals.
masterdecoder
- AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
MAIN_TX_V10
- 8路视频光端机的VHDL源码，此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。-8-channel video PDH in VHDL source code
MAIN_RX_V10
- 8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
jcq
- vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
LCD
- lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source
sd_hd_sdi_demo
- lattice的SDI DEMO板工程源代码，HD/SD自适应，内有彩条自产生源-designed for lattice sdi