资源列表
jishuqi
- 各种功能计数器利用数字电路技术数出给定时间内所通过的脉冲数并显示计数结果-Features the use of digital circuit technology a few counters for a given period of time the number of pulses passed by the count and display the results
rs232
- 使用VERILOG 代码实现的RS232 发送功能，接收一个字符马上回送回来-The RS232 using VERILOG code sending, receiving and sent back immediately return a character
multi
- 这个只是在vhdl中符合4bit adder的乘法code内带test 可放心使用都是小弟已经检测过的-This just in line with 4bit adder vhdl multiplication code can be freely used within the zone test are brother had been detected
VGA_IP
- VGA IP used to connect the FPGA and VGA
baijinzhi
- 利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
lms verilog
- lms veriog程序，不错的代码
VHDLSPI
- FPGA实现的SPI串行通信 可以方便的与微控器建立通信-SPI FOR FPGA COMMUNICATION
DecoderSync
- 本程序用来分离出行同步，列同步和场同步信号，分离后可以得到Hs,Vs和，Fs三个同步信号-This procedure is used to separate travel synchronization, the column sync and field sync signals can be separated Hs, Vs, and, Fs 3 sync signal
RS232
- 基于sopc ep2c5开发板的rs232例程-On sopc ep2c5 development board rs232 routines
statemechine
- We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine f
shift_reg
- Shift Register VHDL program developed in Modelsim