资源列表
Synthesizable_FIFO_verilog
- Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is
Content_Addressable_Memory
- Content Addressable Memory 的verilog源代码。经过modelsim仿真。
VerilogHDL_advanced_digital_design_code_Ch4
- Verilog HDL 高级数字设计源码 _chapter4
VerilogHDL_advanced_digital_design_code_Ch5
- Verilog HDL 高级数字设计源码 _chapter5
VerilogHDL_advanced_digital_design_code_Ch6
- VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6
VerilogHDL_advanced_digital_design_code_Ch7
- VerilogHDL_advanced_digital_design_code_Ch7 Verilog HDL 高级数字设计 源码ch7
div
- VHDL任意整数分频程序，只要讲n换成需要的数字就可以了！
veriloggoldenreferenceguide
- verilog golden reference guide.pdf
geleicounter
- 开发环境是FPGA开发工具，格雷码计数器的VHDL程序
xilinxUSB
- XILINX USB程序
VerilogHDL_advanced_digital_design_code_Ch8
- VerilogHDL_advanced_digital_design_code_Ch8 VerilogHDL高级数字设计源码Ch8
VerilogHDL_advanced_digital_design_code_Ch9
- VerilogHDL_advanced_digital_design_code_Ch9 VerilogHDL高级数字设计源码Ch9