资源列表
FIR
- FIR filter in verilog for xilinx ise design suit
IIC_Verilog
- I2C接口代码，v e r i l o g(The code of I2C interface, verilog HDL)
djvcb
- Optimization class contains several simple sample programs, On neural network control, Noisy pulse correlation detection signal.
并行滤波器实现
- matlab和FPGA实现并行滤波器，为书籍附源码，禁止用于商业用途哈，交流学习使用()
denali_mem_model_example.txt
- Example format of Denali memory models initial memory file content for byte adressable Flash memory
wARM
- 著名的wARM源代码，作者吴瑞祥，Verilog HDL源代码。(Famous wARM source code, author Wu Ruixiang Verilog, HDL source code.)
xapp502配置例程
- FPGA配置例程，VHDL语言，使用CPLD对FPGA进行配置(The FPGA configuration routine, VHDL language, using CPLD on the FPGA configuration)
counter
- Counter example for FPGA with VHDL
ex1_601
- 该程序可产生周期脉冲，脉冲宽度及周期大小可通过改变相关数值调节。(The program can generate periodic pulse, pulse width and cycle size can be adjusted by changing the correlation value.)
Verilog led
- Xilinx ISE开发平台实现4位的led灯循环点亮源代码，测试文件及约束(4 bit LED lamp cycle lighting)
information_box_code1.10
- jibengongnengverilog(jibengongneng verilog)
key_filter
- Verilog实现按键滤波，亲测可用，有需要的可以下载看看(Verilog to achieve key filter)