资源列表
fenpinqi11
- 基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)-divider based on FPGA design, has adopted the simulation (VHDL language)
TrafficLights_VHDL
- 交通灯信号控制器，VHDL语言编写，已实验通过，具体见RAR注释-traffic signal controller, VHDL language, experiment, see specific RAR Notes
riscmcu
- 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
UP3_CLOCK2
- UP3开发板上的时钟控制源代码文件，VHDl编写-degrading development control board clock source documents, prepared VHDl
steppermotorVHDL
- 一种全新的VHDL控制步进电机驱动代码，以供学习-a new VHDL controlled stepper motor driver code for learning
VHDLcontrolCurentmotor
- VHDL设计直流电机的典型例子，适合教学或自学案例-VHDL design Motor typical example, for teaching or self-Case
VHDLdesignGame
- 用VHDl设计一个小游戏的例子，适合教学或自学使用-VHDl design with a small example of the game, suitable for use or self-teaching
VHDLdesignURA
- 用VHDL编写的URAT程序，适合教学或自学使用-VHDL URAT prepared by the procedures for the use of teaching or self -
jiaotongdengcodes
- 实例制作的一个有关交通灯的VHDL代码，从各模块到顶层文件的代码一一列出，详细周到，附带仿真波形图和芯片管脚锁定的相关内容，绝对物超所值。-produced an example of the traffic light VHDL code, from the module to the top of the document sets out a code on January 1, thoughtful details, fringe simulation waveform map and
PWMnios
- niosPWM可以在SOPC builder中实现PWM功能的自定制，通过PWM口可实现对电机的调速。-niosPWM SOPC builder can achieve PWM function of customized, PWM through the mouth can be realized right motor speed control.
liangzhu
- 基于max—plus2开发环境，设计的《梁祝》演奏曲-based max-plus2 development environment, the design of the "Butterfly Lovers" concert song
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding