资源列表
T65_v301
- 微处理器核源码 like 6050 单片机-source like nuclear microprocessor 6050 MCU
ACCUME
- 强调Verilog代码编写规范，经常是一个不太受欢迎的话题，但却是非常有必要的。 每个代码编写者都有自己的编写习惯，而且都喜欢按照自己的习惯去编写-stressed Verilog code-writing norms, is often not a popular topic, but it is very necessary. Each has its own code writers in the preparation habits, but like their own habit
verilogexperance
- verilog硬件描述语言进行开发的一些实际经验-Verilog hardware descr iption language for the development of some practical experience
clk_divide_3
- VHDL语言编写三分频，可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
quartusii
- 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
calendar_clock
- 用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能-using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
88_arms_counter
- vhdl源程序,可在quartus中编辑测试，仿真。-VHDL source code can be edited in Quartus test, simulation.
68_alarm_controller
- vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
78_alu_input
- vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
key_scan1
- 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
ProgramText
- we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.-we will use the cables Spartan3 FPGA design to a specified counter using the VHDL language.
hdb3_VHDL
- hdb3 using language VHDL-Indoor using VHDL language