资源列表
32fenpinqi
- 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。多指正，交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
CLKCP01
- 液晶显示器320*240脉冲实现，每出现12个clk出一个字节脉冲，每出现40个字节脉冲出一个行脉冲。240行结束出一个帧脉冲.-LCD 320 * 240 pulse realized there every 12 clk byte out a pulse, with each 40-byte burst out a pulse line. 240 firms from the end of a frame pulse.
7_4859_1
- 卡内基梅陇大学verilog课程讲义,希望大家能够喜欢！-Verilog University of Paisley and Adams Carnegie Course Training Manual, we hope to love!
44vhdl
- 44个vhdl实例 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O exte
T80_v300
- t80 vhdl source code -t80 VHDL source code
unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164
hiervhdl
- Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
T65_v301
- 微处理器核源码 like 6050 单片机-source like nuclear microprocessor 6050 MCU
ACCUME
- 强调Verilog代码编写规范，经常是一个不太受欢迎的话题，但却是非常有必要的。 每个代码编写者都有自己的编写习惯，而且都喜欢按照自己的习惯去编写-stressed Verilog code-writing norms, is often not a popular topic, but it is very necessary. Each has its own code writers in the preparation habits, but like their own habit
verilogexperance
- verilog硬件描述语言进行开发的一些实际经验-Verilog hardware descr iption language for the development of some practical experience
clk_divide_3
- VHDL语言编写三分频，可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
quartusii
- 推荐!!!!!学ASIC相当不错的教程!!!!还是可以看看的-recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!