资源列表
GF乘法器
- 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
spiflash
- SPI接口实现，对SPI写，擦出等功能操作，此代码在板子上进行验证过，没有任何问题(SPI interface implementation, write to SPI, wipe out and other functional operations, this code has been verified on the board, there is no problem.)
LaSaNewNB_M88E1111_TCP1000mhz
- 用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核(With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core)
ALU32
- 采用booth算法，实现了32位的ALU。(The 32 bit ALU is realized by using the Booth algorithm.)
北航MIPS多周期
- 多周期流水线处理器的verilog实现。(The Verilog implementation of a multi cycle pipelined processor.)
1
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
图像中值滤波FPGA实现V1.0
- 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
Vivado 2016.4 SRIO License
- Vivado 2016.4 SRIO License,已经在Vivado 2016.4 测试通过，可以生产位流。其他版本没有测试，估计也是可以用的(Vivado 2016.4 SRIO License, which has been passed in the Vivado 2016.4 test, can produce a bit stream. The other versions are not tested, and the estimates are also available.)
以太网控制器Verilog源码(含有MAC,MII接口)
- 使用verilog语言完成MAC层代码的编写(Using the Verilog language to write the code of the MAC layer)
spartan6_GTP
- 基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)
硬件描述语言Verilog(第四版)
- 《硬件描述语言Verilog》书籍第四版(Hardware descr iption language Verilog Book Fourth Edition)
ECG_ADS
- ads8684四路通道采样驱动程序，并且有简单的注释说明，能够根据需要修改模拟信号的采样范围(ads8684 drivers(verilog))