资源列表
fpga-b210-verilog
- usrp系统,B210产品的FPGA源码,还是比较有价值的。(The USRP system, the FPGA source of the B210 product, is still more valuable.)
CAR_LI2
- DE1-SOC实验开发板和Verilog HDL语言的交互式程序作品,选择避障小车作为课程设计题目,并根据选题制定了如下设计需求: 1.能实现基本的避障小车功能,即躲避障碍,变速,计分,计时显示游戏开始、进行和结束画面; 2.能实现人机交互功能,玩家可通过外接键盘或DE1-SOC开发板自带按键和开关操作小车转向; 3.能通过VGA在显示屏中显示,并且能达到5Hz的刷新频率; 4.能实现自定义小车和障碍物皮肤的功能;(DE1-SOC experiment development board
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码,验证过,有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Single_cpu
- 单周期CPU自己课程大作业做的,亲测好用,verilog语言,适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
shuzhizhong (1)
- 数字时钟的FPGA设计,对学习FPGA有很大的帮助,希望大家能采纳(FPGA design of digital clock has great help for learning FPGA. I hope everyone can adopt it.)
Vivado_2037
- vivado 2015.4 lisence
lmf
- 在ISE下,FPGA产生线性调频信号,并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
STM32迪文串口屏
- 迪文屏串口程序,自己写,可以移植,用于STM32F1xx系列ARM,可以方便移植使用。 (DWIN DGUS programm used to STM32F1xx.)((DWIN DGUS programm used to STM32F1xx.))
src
- 基于AXI 总线的可配置脉冲计数器,可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
zcu102_exp_1
- 给予Xilinx系列zcu102开发板,完成了一个基本的project,实现了PS 端对PL 端的控制,并在PL端自己生成IP,是初学者很好的学习模板。(Xilinx series zcu102 development board, completed a basic project, the PS end to the PL control, and the PL end of the generation of IP, is a good learning template for begi
try
- 利用xilinx公司开发的vivado平台中的IP核-加法器,实现加法(The addition of IP core adder to the vivado platform developed by Xilinx is applied.)
crc32
- crc32的实现,循环冗余校验的32bit校验结果。(The implementation of CRC32 is the result of 32bit check of cyclic redundancy check.)