资源列表
ffteight
- fft eight point in ccs
RTL
- FPGA复位总控制,在工程中用于复位的关键程序-RST_N control based on FPGA
intf_wrapper
- This a vhdl code for router code for testing write and read transfers code-This is a vhdl code for router code for testing write and read transfers code
KEYS
- 在ISE环境下按键子程序完成多个独立按键的控制-The ISE environment keys subroutines multiple independent control keys
traffic
- verilog编写的十字路口交通灯控制程序，每个方向四盏灯，红黄绿和左拐-verilog prepared crossroads traffic lights control procedures in each direction, four lights, red yellow and green and turn left
divide
- 用veriog实现的任意位数的除法，在modelism中验证过了已经。-Implementation division with verilog.
syncount
- synchronous counter in verilog
dds
- 高精度高速正弦波生成，正弦波相位和正弦波频率可调。-make sin
PS2_Controller
- verilog hdl 实现的PS2控制模块-verilog hdl PS2
MUX
- VHDL Code for 4:1,2:1 MUX using when statment
music.v
- 用VHDL硬件描述语言在CPLD实现播放音乐-VHDL hardware descr iption language used for playing music in the CPLD
spi_slave
- SPI的verilog源代码，可以和DSP2812通信，已经试过，可行。-SPI verilog source code