资源列表
Vhdl1
- VHDL语言编写Verilog，实现数码管上数字循环显示-VHDL language Verilog, to realize the digital tube display digital loop
3Digit_7segment_ind_decoder
- 3 Digit BCD to 7 segment indicator decoder
counter
- 从0到14的计数，当然你改动下源程序，计数范围可以扩大。还带有清零的功能！-From 0 to 14 counts, of course, you change the next source, counts could be expanded. Also with the Clear function!
Soda_Machine
- drink machine finite state machine
ad9850
- AD9850的控制程序，用于产生各种频率的正弦信号-AD9850 control program, used to generate sinusoidal signals of various frequencies
mul8
- designing of 8 bit mulitiplier using verilog code
dengjingdupinglvji
- 设计一个用等精度测频原理的频率计。 频率测量范围1~9999； 其精度为 ； 用4位带小数点数码管显示其频率； 并且具有超量程、欠量程提示功能； -Such as the design of a precision frequency measurement using the principle of the frequency meter. Frequency measuring range 1 ~ 9999 its accuracy 4 with a dec
seven
- 基于VHDL实现输入控制7段数码管的代码，分别用逻辑表达式法和真值表法实现。-VHDL-based implementation of digital control input control 7-segment code, respectively, a logical expression method and truth table method to achieve.
VHDL
- 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
halfadder
- vhdl code for half adder using libero software
TLC
- traffic light controller
dpram_anu
- true dpram with using shared variable