资源列表
LPLFSR
- LPLFSR for low power pattern generation.
fir_memory
- 用memory编写的verilog代码，可用于工程应用，已经过仿真-Verilog code written with the memory can be used for engineering applications, has been simulation
clk_111k
- Clock baud rate modifier
vhdlcodes2
- VHDL coding for a 4 bit comparator in structural and behavioural modelling.
licznik8bit
- 8 bit counter created in vhdl as a program to complete one of my study case.
1
- 本程序成功描述了如何用单片机对温湿度传感器进行控制-This procedure describes how to successfully use the microcontroller to control the temperature and humidity sensor
Counter
- best simple counter for verilog modelsim6.5
s2p.rar
- 串并转换功能，采用VERILOG语言编写，包括测试文件，与大家分享，供大家参考,SERDES function, the use of language VERILOG, including the test documents to share with you, for your information
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
fpga-3
- LED with following two modes. (A) Light Mode: (sw==0) (B) Shift Mode: (sw==1)
fifolifo
- fifo filo verilog 程序！先入先出数据存储器的程序和先入后出程序！-fifo filo verilog program! First in first out data memory of the program!
8-bit-Multiplier
- 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier