资源列表
ade
- 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
FIR2
- 以VERILOG语言描绘的用TLC549和TLC5615的数字低通滤波器的程序-VERILOG language used to describe the TLC549 and TLC5615 digital low pass filter process
downsizer
- A FSM that extracts the 18 LSB out of a 128 bit vector and forwards it as a 18 bit vector.
PPS
- 脉冲宽度可配置，输出不同脉宽值，启动后输出-The pulse width can be configured with different pulse width, output value
div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
multiplier_csa
- 8 bit Multiplier, CSA type
alu
- 加法器源码 CPU设计专用 VHDL实现-Source adder VHDL CPU designed to achieve specific
ccd
- TCD1501D驱动程序 对线阵CCD传感器TCD1501驱动编程-The TCD1501D driver linear CCD sensor TCD1501 driver programming
screw
- 一个好用的扰码器，主要用在光纤通信上面。因为为了保持送给光模块的信号不是全1或者全0-A nice scrambler, mainly used in optical fiber communication above. Because in order to maintain the optical module of the signal is not sent to all 1 or all 0
PSKcodeconversion
- 利用硬件描述语言VHDL实现PSK信号相对码和绝对码的转换-Two VHDL programs to realize the PSK signals conversion between absolute and relative code
analog.c
- jfwletjwevmyrejemrukrk iptyik 67koi