资源列表
uriscram
- RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain.
johnson_encoding_angle
- An FSM using VHDL and Johnson state encoding for states
adc
- adc code in vhdl. by suman, praveen
timing1
- 根据所输入的参数值对标准时钟进行分频，产生特定频率的时钟-this is code that can produce a some certern counter,related to the parment that you imput.
drink_sell_machine
- 用verilog HDL编写的投币机，能实现单种饮料的够买找零-Written in verilog HDL slot machines, enough to buy a single beverage give change
gps_code_gene
- GPS信号C/A码生成器，能够实现gps接收机中c/a码的剥离。-GPS signal C/A code generator is able to achieve a GPS receiver C/code peeled.
fir
- 滤波器的vhdl实现 滤波器的vhdl实现
多路选择器
- 由3-mux和4-mux组成12-mux的verilog编码
signal_generator
- 基于vhdl的多功能函数信号发生器的设计，能实现三角波、方波、正弦波。-VHDL-based multi-function signal generator design, can achieve the triangular wave, square wave, sine wave.
qudoudong
- 多按键去抖动电路VHDL源码，按键个数参数化，每个按键处理调用了上面的模块：-Many buttons to dither circuit VHDL source, the number of key parameter, each key, the call to the treatment of the above modules:
uart_if
- ram source read mode UART CODES.
cdkz
- vhdl编写的彩灯控制程序，比较简单，仅供初学者参考-vhdl prepared by the Lantern control procedures are relatively simple, reference is for beginners