资源列表
NewFolder
- Verilog code for RTC
pulse_generating
- 采用VHDL语言实现输入一定的数字量，从而输出一定的频率可调的脉冲，可以与单片机接口，实现对特定对象的控制-VHDL language used to achieve a certain degree of digital input, so the frequency of certain adjustable output pulse, with the single-chip interface, the achievement of specific targets for the co
bcd_sev
- Code to display Seven Segment
ovsf
- 基于FPGA的OVSF树的设计，在WCDMA中应用比较多-OVSF tree FPGA-based design, the more WCDMA application
adda_test
- xilinx spartan3 读写adc程序-xilinx spartan3 read adc program
div
- restoring divider in verilog
RELOJES
- SHOWS HOW TO CONFIGURE A DCM ON A SPARTAN FPGA
non--restoring
- it is dividing non restoring algorithm implementation using verilog language.
csa3
- carry save adder block3
Example-2-1
- 编译过正确的fpga开发实例，很是适合也新手入门。fpga开发新手间的交流-fpga
2
- simple code of some kind of base decoder based on verilog
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example