资源列表
COUNTER
- 对外部输入的高频脉冲信号进行分频，应用于FPGA/CPLD .-External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
key_scan
- verilog 键盘扫描,数码管显示程序，没有加消抖-verilog keyboard scanning, digital tube display program, there is no increase in consumer Buffeting
UniversalRegister
- 普通的缓冲器 这种设计是一个普通的缓冲器，可以做一个直接的缓冲器，也可以做一个双向的转移缓冲器，还可以做一个递增的计数器和递减计数器-Universal Register This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
MEGA128ADC
- 采用MEGA128内部AD转换器采集数据，兵通过LED数码管显示出来，是学习 MEGA128的好例子-MEGA128 internal AD converter using the data collected, soldiers come through the LED digital display, is a good example of learning MEGA128
randomization
- 伪随机序列应用设计:利用verilog代码实现伪随机信号的产生-Pseudo-random sequence application design: the use of pseudo-random signals verilog code generation
key_led
- 基于xilinxFPGA测试通过，按键消抖动，verilog编写，控制流水灯-Based xilinxFPGA test, the key jitter elimination, verilog prepared to control water lights
iis_m_2
- iis主模块，实现并行数据转成串行数据和音频数据传输的功能。-iis main module, parallel data to serial data transfer and audio data transmission capabilities.
TLC
- Vhdl code for traffic light controller
sin_cos_module
- Verilog实现的cordic算法的计算sin，cos值得模块，使用rom，代码简洁有效。-Verilog implementation of the cordic algorithm of computing the sine and cosine worth module, use of ROM, the code is concise and effective.
fpdiv_vhdl
- 四位除法器的VHDL源程序-four division of VHDL source
FINAL_OUT.VHD
- this is a vhdl program to test your LCD
TestFre
- 通过时钟分频，用PWM脉冲调宽来控制LED灯亮度的强弱，改变PWM的占空比来实现恒流LED的亮度强弱控制-By the clock frequency, pulse width modulated using PWM to control LED brightness light intensity, changes in PWM duty cycle to achieve constant current LED brightness intensity control