资源列表
sqrt
- 用verilog实现的开2次方，已经在modelism中经过验证，其时间周期不固定。-Implementation open square with verilog.
binbcd8
- Binary to BCD conversion in VHDL for implementation in FPGA
BCDto7Segment
- vhdl bcd to seven segment
3-1
- 自动卖报机，5分一份，有1，2，5分类型的硬币。verilog状态机
encode
- 8位优先编码器。 8位优先编码器。-8-bit priority encoder. 8-bit priority encoder. 8-bit priority encoder.
Register8bits
- Register 8 bits VHDL code
array_mult
- array multiplier in vhdl
paixu
- 用冒泡法对16个数据进行排序，并将结果存于固定地址。跑马灯，及循环点亮程序-With the method of bubbling 16 data to sort and will result in fixed deposit address. Scrolling, and circulation of light up the program
verilog_ad7671
- 基于FPGA的AD7671控制代码，是基于verilog语言的，很实用，希望对大家有所帮助-AD7671 FPGA-based control code is based on verilog language, it is practical, we hope to help
ZZ
- 基于VHDL硬件描述语言，对CPSK调制的信号进行解调-cpsk feichanghaoyong nizijimanmankan
HDB3Decoder
- 这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
fast_divider
- 快速除法器，采用循环移位相减算法。 已经通过仿真。-Quick divider using cyclic shift subtraction algorithm. Simulation has been passed.