资源列表
CRC
- 一個CRC-12計算的串入式電路並下載至FPGA電路板-FPGA CRC-16
h_adder
- 一个二位全加器的VHDL实现程序，能够完美在Quartus上运行-a h_adder write in VHDL，can work well on Quartus
die
- die game implimented by haneesh indian
lfsr
- simple PRBS generator using verilog hdl
ra_str_gen1
- ripple with studture modeling vhdl file
duanx
- 实现超简洁、超清晰的 任意整数分频器功能，完全自己编制的。代码清晰了然，且占用自然少。完全适合调用。-Achieve ultra-simple, ultra-clear any integer divider function fully prepared in. Code is clearly understood, and naturally less occupied. Perfectly suited to the call.
sinewave
- Code for sine wave generation
3-1
- 1,2,5分钱 自动报纸售卖机 verilog写的-1,2,5 cents a newspaper vending machines, automatic writing verilog
shape
- 滤波器设计，利用中值法完成的梯形滤波的算法，可用于谱仪的滤波器-filter verilog
MACH_DEM_SAN_PHAM
- Card count product display led 7 segment
LPF_module
- 用verilog实现带宽可调的低通滤波器-Verilog to achieve the low-pass filter with adjustable bandwidth
FASwitch
- Full Adder Design in Switch level Modelling using Verilog