资源列表
DDS_sine
- DDS扫频信号源的FPGA实现，有的是verilog编写，欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
ADCODE
- 用FPGA控制双ADC0809读写，用于双AD热备控制，用verilog实现-FPGA control with dual ADC0809 read and write, hot standby control for double AD, with verilog implementation
ds_test12
- HDL语言初始化 ds18b20，数码管温度显示，蜂鸣器报警-HDL language initialization ds18b20, digital temperature display, buzzer alarm
fpga_training
- fpga 入门教程，适合与fpga初学者，使用quartus环境。推荐-fpga Getting Started tutorial for beginners with the fpga, using quartus environment. Recommended
SOBLE_VGA
- SOBEL_VGA 黑金AX301开发板， 通过摄像头OV7670采集图像，通过FPGA进行边沿检测算法,最后通过VGA进行显示。-SOBEL_VGA u9ED1 u91D1AX301 u5F00 u53D1 u677F uFF0C u901A u8FC7 u6444 u50CF u5934OV7670 u91C7 u96C6 u56FE u50CF uFF0C u901A u8FC7FPGA u8FDB u884C u8FB9 u6CBF
ds1302_spi
- 这个程序是基于fpga和ds1302的verilog代码，代码简洁明了，容易看懂。推荐大家学习-This program is based on fpga and ds1302 verilog code, code simple, easy to understand.Recommend everybody to learn
sdram1
- 定制sopc系统。使用sdram控制器。在nios ide上执行存储器的读写操作。-To customize sopc system. Use sdram controller. In the the nios ide perform memory read and write operations.
DE3_usermanual
- Terasic de3 for intel quartus ii manual
vga_driver
- 基于EP3C16的VGA显示驱动工程。时钟40M，图片存储在FPGA内部的ROM中，VGA显示器分辨力为800*600*60Hz，存储图片需要800*600点（bit），由于EP3C16的ROM不够大，ROM中存储内容为8bit*30000；显示器内容为上下半屏分别显示ROM中的内容，显示图片相同。ROM中的内容由地址线的变化来控制。-Display driver works based EP3C16 of VGA. Clock 40M, pictures stored in the ROM o
Goujian
- 搭建FPGA嵌入式系统 FPGA Design - Best Practices- FPGA Design- Best Practices
FPGA-2C35-EDA-bochuang
- UP-CUP FPGA2C35-II型平台EDA实验v4.3； FPGA-eda部分基础常用实验代码。-UP-the CUP FPGA2C35-II platform EDA Experiment v4.3 the FPGA-eda part, the basis of the commonly used experimental code.
ProtelDXP
- PROTEL工具，强大的EDA设计工具，提供原理图PCB VHDL等项目设计能力-SCH PCB