资源列表
binary
- binary state machine encoder
mo12_counter
- 基于FPGA的VHDL程序实现模12计数器-FPGA VHDL model12counter
di1
- 计数器的设计，可以累加计数。实现计数功能，代码功能如下所示。-Count-counter design. Counting function, the function of the code is shown below.
inout-vhdl
- c p u 读inout 端口的vhdl 程序-Read inout port vhdl program
encoder
- RS(7,3,4)，码长七位，信息位三位，纠错位四位，经过验证成功-RS (7,3,4), the code length of seven, three of information bits, bit error correction four proven successful
PSKcodeconversion
- 利用硬件描述语言VHDL实现PSK信号相对码和绝对码的转换-Two VHDL programs to realize the PSK signals conversion between absolute and relative code
analog.c
- jfwletjwevmyrejemrukrk iptyik 67koi
CLK_DIV
- verilog HDL写的时钟通用计数分频程序，设置系统时钟，并根据目标时钟，设置分频系数即可得到目标时钟。已实际测试可用。-verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the targ
uart_trs_state
- 本程序是串口的FPGA产生程序，希望在此能够给与大家共享-This program is a serial FPGA generator, I hope to give everyone shared this
fulladder
- this is fulladder 1bit with testbench
pwm
- 使用VHDL实现可调的PWM控制器，便于初学者学习-Use VHDL to achieve an adjustable PWM controller, easy for beginners to learn