资源列表
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.A
- Wiley IEEE PRESS RTL Hardware Design using VHDL 2006
Learning-VHDL-with-example
- 学习VHDL，从入门到精通，包括学习的书籍资料和相关例程分析。-Learning VHDL, from entry to the master, including the study of books, information and case studies.
ml605_FMC_Si570_Prog_rdf0047_13.4_c
- 该源码是基于xilinx ml605开发板扩展接口FMC的设计，在开发板中插入子卡，程序在开发板中测试通过。-The source is based on xilinx ml605 development board FMC expansion interface design, the development board daughter card is inserted, the program development board test.
3ram_ram
- 程序实现了FPGA内部RAM之间的数据传输。采用了3片RAM+RAM的结构形式。已通过调试-Procedures to achieve the data transmission between the FPGA internal RAM. Uses 3 RAM+RAM structure. Has passed through debugging
FPGA对W25Q16读写
- FPGA对W25Q16读写FPGA对W25Q16读写FPGA对W25Q16读写FPGA对W25Q16读写
EDA
- 1602显示的数字钟 功能请详看文档 1602显示的数字钟 功能请详看文档-1602 clock 1602 clock 1602 clock
clock
- 基于verilog简易数字钟，能够做到计时，闹钟，倒计时等功能。(Based on Verilog simple digital clock, can achieve time, alarm clock, countdown and other functions.)
prj_2
- a practical project using blk_mem_gen_v7_1_Veriloge
09_vga
- FPGAvga的使用完整工程例子，芯片型号是 EP4CE6F17C8N(FPGAvga's use example, the chip model is EP4CE6F17C8N)
vga_driver
- verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK-verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK
TR4_GPIO1_D8M
- 友晶科技的TR4的开发板，接上D8M摄像头的程序 输出的是MIPI解码后的10位数据 内带signaltap仿真结果和连接图(The development board of TR4, the D8M camera program. The output is the 10 bit data after MIPI decoding. include signaltap simulation results and connection diagrams)
EDA
- vhdl语言编写的交通灯。有程序有电路图。-The VHDL language the traffic lights. There is a program to the circuit diagram.