资源列表
lab10000
- detection of the following sequence ‘10110110’in VHDL
cout60
- 用VHDL语言编写的60进制计数器，初学者使用-VHDL language with the 60 binary counter, for beginners to use
12dac
- 自己编的12位dac 不过需要外接滤波器才可以看得更好些-a 12bit dac need a lpf which can view clearly
ringcounter
- ring counter for vhdl code
E1-Program_With_Functions
- exercise lab for students
flowbyte_shifter
- Module that can shift stream by one or more bits. It can be use for sinhronization in STM.
codelock
- VHDL语言编写的数字密码锁，异步清零，带有开锁，关锁，修改密码的功能-VHDL language digital code lock, asynchronous clear, with a lock, lock, change the password function
f_de_ck564
- 根据数据校准时钟，实现频率时钟校准，能够使数据准确输入进入ram-clk jiaozhun shixian shujuzhunqueduru
dial
- verilog 写的v5板子按键的测试程序 可以直接使用 已测试-this is a code applied for dial in v5
verilog-HDL-Divider
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
shift_1x64_vhd
- register shifter of 64bits
divby4.5.v
- This Divider by 4.5.-This is Divider by 4.5.