资源列表
CON_AD
- 控制AD采样的程序,希望对大家能有所帮助!不对之处请多多指导!-I think it is a goog pragram ,I hope it is good for you !
light_controller
- 用HDL语言编写彩灯控制程序： 用状态机实现一个循环彩灯控制器，该控制器控制红、绿、黄三个发光管循环发亮，要 求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。程序所用时钟的频率为1HZ。-Lantern with HDL language control program: A state machine to achieve a circular lantern controller that controls red, green, yellow three LED lights c
std_ecl_converter
- Std Logic to ECL Logic (IHP technologie)-Std Logic to ECL Logic (IHP technologie)
New-WinRAR-archive
- A VHDL code to program a counter from 0-2-A VHDL code to program a counter from 0-255
psubadd8
- 4位减法器，可以完成4位数的减法功能，也可以完成更高一层的8位减法器。-4 subtractor, can complete a four-digit subtraction, you can complete a higher level of 8-bit subtractor.
ppm
- 实现PPM编码，经测试，准确可用。现在正在调解码器。不久也可以上传。-Implement PPM encoding, tested and accurate available. Now mediate codec. Can also be uploaded soon.
MUXER
- SHOWS THE SIMPLEST WAY TO CREATE A SIMPLE MUX IN VHDL-SHOWS THE SIMPLEST WAY TO CREATE A SIMPLE MUX IN VHDL...
word
- 英文显示电路显示0到f 的十六进制计数器-English display circuit
vga.v
- 基于altera公司的maxii epm240t100c5系列的 实现了 vgA接口控制-Based on the the altera Company' s maxii epm240t100c5 series realized vgA interface control
jiance1
- 3异或条件输出 周期的伪随机数生成器伪随机数 -The XOR output cycle pseudo-random number generator
addercs16.v
- 这是自己写的 16 bits carry select adder 的verilog的代码，如果有用fell free to download-It is 16 bits verilog write their own code to carry select adder, if a useful fell free to download
CCD_Sim
- 用verilog HDL语言编写的面阵CCD相机输出图像程序。-The CCD camera output image process using Verilog HDL language.