资源列表
5
- 七段字符显示器逻辑功能的VHDL语言程序，本程序采用IF语句形式-VHDL language program of the seven-segment character display logic functions
fsk
- 用Verilog语言实现FSK调制-FSK modulation with the Verilog language
piso_beha_tb
- parllel toserial out test bench
led
- FPGA实现led 流水灯,时间较长，循环闪烁，效果十分漂亮-led light
keyscan3
- 键盘扫描 以及输入后在LED 上的显示数字是无人分配【是大牌fks东平干净哦耍大牌企鹅王如图七二五体弱配挖潜普通孤儿我陪你 -After scanning the keyboard and input on the LED display digital distribution is no big fks Dongping 【is clean and the king penguins Oh diva seven hundred twenty-five frail figure with
jicun
- 32位32个寄存器组程序设计，用vhdl语言-module registers071221049 ( input [4:0]s1,s2, input [4:0] wd, input [31:0] data, input wre, clk, input he,hc,le,lc, output [31:0] out1, output [31:0] out2 )
Gate.level.adder
- Verilog 门电路级别的全加器，测试通过-Verilog Gate Level adder and testbenck
ff_const_mul
- 常系数有限域乘法器，verilog DHL源码-Constant coefficient finite field multiplier, verilog DHL source
buffterfly_radix4
- 16点的FFT蝶形运算，用于快速傅里叶变换并行实现，基于verilog语言编写，matlab仿真验证-a method based on 16-point fft butterfly,used to make fast fourier transform,language is verilog.
uartfifo
- uart 通用异步收发器 verilog 代码，实现自收发功能，quartus运行有效。-uart universal asynchronous transceiver verilog code, since the transceiver function, quartus operating effectively.
multiplexor
- multiplexor 3x1 bites is done by me on cla-multiplexor 3x1 bites is done by me on class
EDA
- EDA小程序，用VHDL语言设计七人表决器，四位加法器。-EDA small program design using VHDL seven people voting, four adder.