资源列表
sine
- 简易的正弦信号发生器，用verilog代码写成-A simple sinusoidal signal generator, written with verilog code
8-Bit-Simple-Up-Counter
- 简单的，计数器，上升沿有效。经过ise13.1测试，完全符合逻辑-Simple, counters, and the positive edge. Tested
ade
- Verilog code for modified serial multiplier
counter
- A 4 bit counter. In the testbench I combine three counters into one. Verilog codes with testbench.
mux-top-module
- Vhdl implementation of Mux module using and gate or gate and with testbench
paral_to_serial
- 用verilog HDL编写的并行接口转串行接口的程序。-The programming of parallel interface to serial interface with HDL verilog.
Filtro
- Digital filter in VHDL
rs_enc
- 这是一个用VHDL编写的RS信道编码程序-This is a VHDL prepared with RS channel coding procedures
movedata
- 按照一定格式把一段数据放在内存上，然后输出在屏幕上-my asm
testt
- 四线电阻式触摸屏控制芯片ads7843的控制方法-touch screen control ads7843
jishuqi
- vhdl简单的脉冲计数器程序，初学者可以用来借鉴，没有错误！经实验验证，完美运行-vhdl pulse counter program, beginners can be used to learn there are no errors! The experiments prove that the perfect run
main
- EP2C35A实验箱基于NIOSII的串行AD_DA编程-EP2C35A experimental box based NIOSII the serial AD_DA programming