资源列表
16szxgq
- 16位数字相关器，通过4个4位相关器和两级加法电路组成
door_state
- 实现自动门的控制,实现其开、关、复位、门开最大、门关最小等功能-Realization of automatic control
binary_to_BCD
- 本人编写的2进制转换为BCD码的verilog程序，绝对可用，已测试通过。-I write binary to BCD verilog program, absolutely free, have been tested.
REG8
- 寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习-VHDL source register. May be a bit simple volume between novice you would like to learn
file_io
- 读写硬盘文件的VHDL仿真例程，该例程能够帮助FPGA设计人员读取硬盘的数据文件输入仿真环境，并且将仿真后的数据存入硬盘-test bench for reading and writing disk files
vsim
- multiplexer 16_1 is a multiplexer with 16 inputs and 1 output.
decision_reg.vhd
- Variable register example
serial
- 串口程序，具有起始位，数据位，停止位（无奇偶校验位）-serial program
qiangda
- 设计的四人多路抢答器，基于vhdl开发环境-this project is based on vhdl
pwmm
- 通过改变占空比，实现8个流水灯渐亮渐暗的功能-By changing the duty cycle to achieve the eight water lights fade function fades
my_VGA
- FPGA驱动VGA显示，通过验证，需要的可以下载。verilog实现-VGA display driven by the FPGA, through validation, need can be downloaded. verilog implementation
PWM-LED
- 根据输入电压改变pwm来调节LED输出光。-adjust PWM to dim LED according to input voltage.